Nonvolatile semiconductor memory cells which require only very small programming currents are of particular interest where it is desirable to minimize the dissipated power in electrically programmable memory matrices (EEPROM). In this category of memory cells are MNOS memory cells and memory cells with an electrically floating storage gate which are recharged via tunnel injector. The latter have the advantage over MNOS memory cells, of having better retention and endurance times. The retention time relates to the period of maintaining the stored data (retention) and the endurance time indicates the number of reprogramming operations (endurance) which can be performed without causing any damage. A memory cell of the last-mentioned kind is described in the technical journal "Electronics" of Feb. 28, 1980, pp. 113 to 117. These so-called "floating gate" memory cells are popular with both users and manufacturers, because their manufacturing technique has a higher degree of compatibility with modern standard technologies.
The "1980 IEEE International Solid-State Circuits Conference, Digest of Technical Papers", pp. 152 and 153, describes an electrically erasable memory matrix comprising memory cells arranged in n rows and m columns. Each of the memory cells contains a tunnel injector which is capable of letting electrons tunnel through a sufficiently thin oxide layer in both directions with respect to an electrically floating storage gate. The injector of each memory cell is connected to a first bit line via the source-drain line of a memory transistor and to a second bit line via the source-drain line of a select transistor, while the control gate of the memory transistor is connected to a programming line. The gate of the select transistor is connected to a row selecting line via which, in a row-wise manner, the n memory cells of each row can be selected. The invention deals with a memory cell of a similar design employing an electrically floating storage gate.
For solving the already previously mentioned problem of reducing the dissipated power it is known to realize the periphery of the memory matrix in accordance with the known CMOS technology with the aid of CMOS gates. Such a solution is described in the "1982 IEEE International Solid-State Circuits Conference, Digest of Technical Papers" (February 1982), pp. 110 and 111. This conventional memory matrix, however, has two properties which do not yet correspond to the desired properties of a pure CMOS circuit:
(1) when reading stored data, the direct current consumed exceeds the reverse current level customary with CMOS circuits; and
(2) the voltage applied to the injector during the zero writing (Wo), effecting a tunneling of electrons from the storage gate into the injector, does not reach the full value of the available programming voltage Vp, but remains therebelow by the amount of the threshold voltage Ut of the select transistor plus the substrate effect voltage.